1 Opening(s)
5.0 Year(s) To 10.0 Year(s)
12.00 LPA TO 30.00 LPA
Exp: 7 to 15 years
Work location: Bangalore/Remote
Key Responsibilities:
Work with system architect to understand the requirements and design efficient RTL implementations targeting FPGAs.
Translate MATLAB models to RTL for hardware realization
MATLAB/Simulink based modelling, simulation and conversion to RTL
Develop RTL architecture and microarchitecture based on algorithm requirements
Implement RTL (Verilog/VHDL/SystemVerilog) for blocks like ORAN, ...