2 Opening(s)
2.0 Year(s) To 6.0 Year(s)
10.00 LPA TO 15.00 LPA
VHDL Job Responsibilities:
Designing High Performance digital blocks for Complex Communication Coding using VHDL.
Hands-on with RTL development (VHDL), simulation, writing test benches, and debug.
Experience with developing timing constraints and running state-of-the-art synthesis tools, timing analysis tools, such as Xilinx Vivado suite.
Participate in module architecture and specification
Block level design verification
Strong hands-on with ...