4 Opening(s)
3.0 Year(s) To 7.0 Year(s)
5.00 LPA TO 20.00 LPA
ASIC verification - Engneer
Individually with/without guidance.
He/She will be involved in developing assertions, RTL development/debugging and formal verification (RTL verification or tool validation).
* He/She will be involved in developing Testcases, Tesplans and reviews of documents and code.
* He/She will be individually responsible for successful delivery to clients for given tasks/module of ...
2 Opening(s)
2.0 Year(s) To 6.0 Year(s)
10.00 LPA TO 15.00 LPA
VHDL Job Responsibilities:
Designing High Performance digital blocks for Complex Communication Coding using VHDL.
Hands-on with RTL development (VHDL), simulation, writing test benches, and debug.
Experience with developing timing constraints and running state-of-the-art synthesis tools, timing analysis tools, such as Xilinx Vivado suite.
Participate in module architecture and specification
Block level design verification
Strong hands-on with ...